module proccore
			(
			 clock, resetn,
			 rDIPSW,
			 INITA, INITB,
			 PORTA, PORTB,
			 rA, rB,

			 INTFLAG,
			 PERIINIT, PERIADDRREG, PERICTRLREG, PERIVALREG
			);

input			clock, resetn;

input	[7:0]	rDIPSW;
input	[11:0]	INITA;
input	[15:0]	INITB;

output	[11:0]	PORTA;
output	[15:0]	PORTB;
output	[27:0]	rA, rB;

input	[7:0]	INTFLAG;

output	[3:0]	PERIINIT;
output	[3:0]	PERIADDRREG;
output	[7:0]	PERICTRLREG;
output	[15:0]	PERIVALREG;

/* Definition of wires for interfacing control path and data path */
wire			zero_a, zero_b;
wire			branch, decabnz, decbbnz;
wire			ioset, loada, loadb;
wire			swait, waitint;
wire			ramp, rsram, rlta;
wire			initperi;

wire			int_tmr;
wire			int_masked;

wire			load_pc, cnten_pc, sclr_pc;
wire			load_opc, load_opr;
wire			load_a, cntdn_a, sclr_a;
wire			load_b, cntdn_b, sclr_b;
wire			load_cntref, cnten_tmr, sclr_tmr;
wire			init_porta, load_porta;
wire			init_portb, load_portb;
wire			sel_portb;
wire	[5:0]	PBADDR;

wire			load_peri, sclr_peri;
wire			load_int, sclr_int, init_peri;

wire			sclr_ltacnt, cnten_ltacnt;
wire			load_podreg;

/*
module ctrlpath
		(
		clock, resetn,

		zero_a, zero_b,
		
		branch, decabnz, decbbnz,
		ioset, loada, loadb,
		swait, waitint,
		ramp, rsram, rlta,
		initperi,

		int_tmr,
		int_masked,
		rDIPSW,
		
		load_pc, cnten_pc, sclr_pc,
		load_opc, load_opr,
		load_a, cntdn_a, sclr_a,
		load_b, cntdn_b, sclr_b,
		load_cntref, cnten_tmr, sclr_tmr,
		init_porta, load_porta, init_portb, load_portb,
		sel_portb, PBADDR
		load_peri, sclr_peri, init_peri,
		load_int, sclr_int
		);
*/
ctrlpath	CTRLPATH1	(.clock(clock), .resetn(resetn),

						 .zero_a(zero_a), .zero_b(zero_b),

						 .branch(branch), .decabnz(decabnz), .decbbnz(decbbnz),
						 .ioset(ioset), .loada(loada), .loadb(loadb),
						 .swait(swait), .waitint(waitint),
						 .ramp(ramp), .rsram(rsram), .rlta(rlta),
						 .initperi(initperi),

						 .int_tmr(int_tmr),
						 .int_masked(int_masked),
						 .rDIPSW(rDIPSW),

						 .load_pc(load_pc), .cnten_pc(cnten_pc), .sclr_pc(sclr_pc),
						 .load_opc(load_opc), .load_opr(load_opr),
						 .load_a(load_a), .cntdn_a(cntdn_a), .sclr_a(sclr_a),
						 .load_b(load_b), .cntdn_b(cntdn_b), .sclr_b(sclr_b),
						 .load_cntref(load_cntref), .cnten_tmr(cnten_tmr), .sclr_tmr(sclr_tmr),
						 .init_porta(init_porta), .load_porta(load_porta),
						 .init_portb(init_portb), .load_portb(load_portb),
						 .sel_portb(sel_portb), .PBADDR(PBADDR),
						 .load_peri(load_peri), .sclr_peri(sclr_peri),
						 .load_int(load_int), .sclr_int(sclr_int), .init_peri(init_peri));
/*
module datapath
		(
		clock, resetn,
		
		load_pc, cnten_pc, sclr_pc,
		load_opc, load_opr,
		load_a, cntdn_a, sclr_a,
		load_b, cntdn_b, sclr_b,
		load_cntref, cnten_tmr, sclr_tmr,
		init_porta, load_porta, INITA,
		init_portb, load_portb, INITB,
		sel_portb, PBADDR,
		
		load_peri, sclr_peri, init_peri,
		load_int, sclr_int,
		INT,
		
		zero_a, zero_b,
		
		branch, decabnz, decbbnz,
		ioset, loada, loadb,
		swait, waitint,
		ramp, rsram, rlta,
		initperi,

		int_tmr,
		int_masked,
		
		PORTA, PORTB,
		rA, rB,
		PERIINIT, PERIADDRREG, PERICTRLREG, PERIVALREG
		);

*/
datapath	DATAPATH1	(.clock(clock), .resetn(resetn),

						 .load_pc(load_pc), .cnten_pc(cnten_pc), .sclr_pc(sclr_pc),
						 .load_opc(load_opc), .load_opr(load_opr),
						 .load_a(load_a), .cntdn_a(cntdn_a), .sclr_a(sclr_a),
						 .load_b(load_b), .cntdn_b(cntdn_b), .sclr_b(sclr_b),
						 .load_cntref(load_cntref), .cnten_tmr(cnten_tmr), .sclr_tmr(sclr_tmr),
						 .init_porta(init_porta), .load_porta(load_porta), .INITA(INITA),
						 .init_portb(init_portb), .load_portb(load_portb), .INITB(INITB),
						 .sel_portb(sel_portb), .PBADDR(PBADDR),
						
						 .load_peri(load_peri), .sclr_peri(sclr_peri), .init_peri(init_peri),
						 .load_int(load_int), .sclr_int(sclr_int),
						 .INT(INTFLAG),
						
						 .zero_a(zero_a), .zero_b(zero_b),

						 .branch(branch), .decabnz(decabnz), .decbbnz(decbbnz),
						 .ioset(ioset), .loada(loada), .loadb(loadb),
						 .swait(swait), .waitint(waitint),
						 .ramp(ramp), .rsram(rsram), .rlta(rlta),
						 .initperi(initperi),

						 .int_tmr(int_tmr),
						 .int_masked(int_masked),

						 .PORTA(PORTA), .PORTB(PORTB),
						 .rA(rA), .rB(rB),

						 .PERIINIT(PERIINIT), .PERIADDRREG(PERIADDRREG),
						 .PERICTRLREG(PERICTRLREG), .PERIVALREG(PERIVALREG));

endmodule